
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
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7
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and IDD in standby
mode depends on the resonator or crystal type.
TIMING CHARACTERISTICS
(V+ = +5V ±5%, VDD = +2.7V to +5.25V, AGND = DGND, fCLKIN = 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA = TMIN to TMAX,
unless otherwise noted.) (Notes 19, 20, 21)
0100
VDD = 3.3V
VDD = 5V
VDD = 3.3V
VDD = 5V
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t10
10
100
ns
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t6
080
ns
INT High Time
tINT
560 / N
x tCLKIN
ns
X2CLK = 1, N = 2(2 x MF1 + MF0)
X2CLK = 1
X2CLK = 0
SCLK Setup to Falling Edge CS
t4
30
ns
SCLK Low Pulse Width
t8
100
ns
10
70
100
ns
VDD = 5V
CS Rising Edge to SCLK Rising
Edge Hold Time
t9
0
ns
(Note 21)
SCLK High Pulse Width
t7
100
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t5
30
ns
280 / N
xtCLKIN
INT to CS Setup Time
t3
X2CLK = 0, N = 2(2 x MF1 + MF0)
0
ns
(Note 8)
RESET Pulse Width Low
t2
100
ns
Master Clock Input Low Time
fCLKIN LO
0.4 x
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Input High Time
fCLKIN HI
0.4 x
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Frequency
fCLKIN
0.8
5.0
MHz
Crystal oscillator or clock
externally supplied for
specified performance
(Notes 22, 23)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
0.4
2.5
CONDITIONS
SCLK Rising Edge to INT High
(Note 27)
t11
200
ns
VDD = 3.3V
SERIAL-INTERFACE READ OPERATION